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IC42S16160 integrated circuit solution inc. 1 dr037-0a 9/05/2003 document title 4m x 16bit x 4 banks (256-mbit) sdram revision history revision no history draft date remark 0a initial draft september 05,2003 preliminary the attached datasheets are provided by icsi. integrated circuit solution inc reserve the right to change the specifications a nd products. icsi will answer to your questions about device. if you have any questions, please contact the icsi offices.
IC42S16160 2 integrated circuit solution inc. dr037-0a 9/05/2003 icsi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated circuit solution inc. features ? single 3.3v ( 0.3v) power supply ? high speed clock cycle time -6: 166mhz, -7: 133mhz ? fully synchronous operation referenced to clock rising edge ? possible to assert random column access in every cycle ? quad internal banks contorlled by ba0 & ba1 (bank select) ? byte control by ldqm and udqm for IC42S16160 ? programmable wrap sequence (sequential / interleave) ? programmable burst length (1, 2, 4, 8 and full page) ? programmable cas latency (2 and 3) ? automatic precharge and controlled precharge ? cbr (auto) refresh and self refresh ? lvttl compatible inputs and outputs ? 8,192refresh cycles / 64ms ? burst termination by burst stop and precharge command ? package 400mil 54-pin tsop-2 description the IC42S16160 are high-speed 256m-bits synchro- nous dynamic random-access memories, organized as 4m x 16 x 4 (word x bit x bank), respectively. the synchronous drams achieved high-speed data transfer using the pipeline architecture and clock frequency up to 166mhz for -6. all input and outputs are synchronized with the positive edge of the clock.the synchronous drams are compatible with low voltage ttl (lvttl).these products are packaged in 54-pin tsop-2. 4m x 16 bits x 4 banks (256-mbit) synchronous dynamic ram
IC42S16160 integrated circuit solution inc. 3 dr037-0a 9/05/2003 pin configurations dqm dq mask enable a0-12 address input ba0,1 bank address v dd power supply v ddq power supply for dq v ss ground v ssq ground for dq pin descriptions clk master clock cke clock enable cs chip select ras row address strobe cas column address strobe we write enable dq0 ~ dq15 data i/o 54-pin tsop-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 vdd vss dq1 5 vssq dq1 4 dq1 3 vdd q dq1 2 dq1 1 vssq dq1 0 dq9 vdd q dq8 vss nc udq m clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss
IC42S16160 4 integrated circuit solution inc. dr037-0a 9/05/2003 functional block diagram c lk c ke clock generator cs ras mode register column address buffer & burst counter cas we command decoder control logic address row address buffer & refresh counter bank b bank a sense amplifier column decoder & latch circuit row decoder data control circuit d q dq m latch circuit input & output buffer bank c bank d
IC42S16160 integrated circuit solution inc. 5 dr037-0a 9/05/2003 pin functions symbol type function (in detail) clk input pin master clock: other inputs signals are referenecd to the clk rising edge cke input pin clock enable: cke high activates, and cke low deactivates internal clock signals,device input buffers and output drivers. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cs input pin chip select: cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras, cas, we input pin command inputs: ras , cas and we (along with cs ) define the command being entered. a0-a12 input pin address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. the row address is specified by ra0-ra12. the column address is specified by ca0-ca8 (IC42S16160) ba0,ba1 input pin bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. dqm, udqm ,ldqm input pin din mask / output disable: when dqm is high in burst write, din for the current cycle is masked. when dqm is is high in burst read, dout is disable at the next but one cycle. dq0 to dq15 i/o pin data input / output: data bus. v dd , v ss power supply pin power supply for the memory array and peripheral circuitry. v ddq , v ssq power supply pin power supply are supplied to the output buffers only.
IC42S16160 6 integrated circuit solution inc. dr037-0a 9/05/2003 absolute maximum ratings (1) symbol parameters rating unit v dd supply voltage (with respect to v ss ) ?0.5 to +4.6 v v ddq supply voltage for output (with respect to v ssq ) ?0.5 to +4.6 v v i input voltage (with respect to v ss ) ?0.5 to v dd +0.5 v v o output voltage (with respect to v ssq ) ?1.0 to v ddq +0.5 v i o short circuit output current 50 ma p d power dissipation ( t a = 25 c) 1w t opt operating temperature 0 to +70 c t stg storage temperature ?65 to +150 c notes: 1. exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc recommended operating conditions ( at t a = 0 to +70c unless otherwise noted) symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ddq supply voltage for dq 3.0 3.3 3.6 v v ih high level input voltage (all inputs) 2.0 ? v dd + 1.2 v v il low level input voltage (all inputs) -1.2 ? +0.8 v notes: 1. all voltages are referenced to v ss =0v 2. v ih (max) for pulse width with 3ns of duration 3. v il (min) for pulse width with 3ns of duration capacitance characteristics (at t a = 0 ~ 70c, v dd = v ddq = 3.3 0.3v, v ss = v ssq = 0v , unless otherwise note d ) symbol parameter max. unit c in input capacitance, address & control pin 5pf c clk i nput capacitance, clk pin 4pf c i / o data input/output capacitance 6.5 pf
IC42S16160 integrated circuit solution inc. 7 dr037-0a 9/05/2003 dc electrical characteristics (at t a = 0 ~ 70c, v dd = v ddq = 3.3 0.3v, v ss = v ssq = 0v , unless otherwise note d ) symbol parameter test condition speed min. max. unit i cc 1 (1) operating current one bank active , cas latency = 3 -6 ? 90 ma burst length=1 -7 ? 80 ma t rc = t rc (min.) t clk = t clk (min.) i cc 2p precharge standby current cke < v il ( max )t ck = 15 ns -6 ? 2 ma (in power-down mode) -7 ? 2 ma i cc 2ps cke < v il ( max ) clk < v il ( max )-6 ?1ma -7 ? 1 ma i cc 2n (2) precharge standby current cs > v cc -0.2v t ck = min -6 ? 55 ma (in non power-down mode) cke > v ih ( min )-7?45ma i cc 2ns cs > v cc -0.2v cke < v il ( max )-6 ?5ma cke > v ih ( min ) all input signals are stable. -7 ? 5 ma i cc 3p active standby current cke < v il ( max )t ck = min -6 ? 10 ma (in power-down mode) -7 ? 10 ma i cc 3n (2) active standby current cs > v cc -0.2v t ck = min -6 ? 65 ma (in non power-down mode) cke > v ih ( min )-7?55ma i cc 4 operating current all banks active cas latency = 3 -6 ? 170 ma (in burst mode) burst length=1 -7 ? 150 ma t ck = t ck ( min ) i cc 5 auto-refresh current t rc = t rc ( min ) -6 ? 270 ma t clk = t clk ( min ) -7 ? 240 ma i cc 6 (3, 4) self-refresh current cke < 0.2v -6 ? 3 ma -7 ? 3 ma i il input leakage current 0v < v in < v dd ( max )?55a (inputs) pins not under test = 0v i ol output leakage current output is disabled dq# in h - z., ?5 5 a (i/o pins) 0v < v out < v dd ( max ) v oh high level output voltage i out = ?2 ma 2.4 ? v v ol low level output voltage i out = +2 ma ? 0.4 v notes: 1. i cc (max) is specified at the output open condition. 2. input signals are changed one time during 30ns.
IC42S16160 8 integrated circuit solution inc. dr037-0a 9/05/2003 ac test conditions (at t a = 0 ~ 70c, v dd = v ddq = 3.3 0.3v, v ss = v ssq = 0v , unless otherwise note d ) parameter rating unit ac input levels (v ih /v il ) 2.0 / 0.8 v input timing reference level /output timing reference level 1.4 v input rise and fall time 1 ns output load condition 50 pf ? v ddq v ddq v out device under test 50p f z = 50 output load conditions
IC42S16160 integrated circuit solution inc. 9 dr037-0a 9/05/2003 ac electrical characteristics (at t a = 0 ~ 70c, v dd = v ddq = 3.3 0.3v, v ss = v ssq = 0v , unless otherwise note d ) -6 -7 symbol parameter min. max. min. max. units t ck 3 clk cycle time cas latency = 3 6 ? 7 ? ns t ck 2 cas latency = 2 7.5 ? 10 ? ns t ac 3 clk to valid output delay (1) cas latency = 3 ? 5.4 ? 5.4 ns t ac 2 cas latency = 2 ? 5.4 ? 6 ns t ch clk high pulse width 2.5 ? 2.5 ? ns t cl clk low pulse width 2.5 ? 2.5 ? ns t cke cke setup time 1.5 ? 1.5 ? ns t ckh cke hold time 0.8 ? 0.8 ? ns t as address setup time 1.5 ? 1.5 ? ns t ah address hold time 0.8 ? 0.8 ? ns t cms command setup time 1.5 ? 1.5 ? ns t cmh command hold time 0.8 ? 0.8 ? ns t ds data input setup time 1.5 ? 1.5 ? ns t dh data input hold time 0.8 ? 0.8 ? ns t oh output data hold time (1) 3? 3? ns t lz clk to output in low - z 1? 1? ns t hz clk to output in h - z 36 37 ns t rc row cycle time 60 ? 60 ? ns t ras row active time 42 100,000 45 100,000 ns t rcd ras to cas delay 12 ? 15 ? ns t rp row precharge time 15 ? 15 ? ns t rrd row active to active delay 12 ? 14 ? ns t dpl data in to precharge 12 ? 15 ? ns t t transition time 0.3 1.2 0.3 1.2 ns t rsc mode reg. set cycle 12 ? 14 ? ns t pde power down exit setup time 06 07 ns t srx self refresh exit time 1? 1? ns t ref refresh time ? 64 ? 64 ms t dqz dqm data out disable latency ?2 ?2 clk t dqw dqm write latency 2? 2? clk t wr write recovery time 0? 0? clk notes: 1. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
IC42S16160 10 integrated circuit solution inc. dr037-0a 9/05/2003 basic features and function description simplified state diagram self refresh mrs mode register set idle auto refresh ref act cke cke b s t power down active power down row active read cke cke read read suspend cke cke read a reada suspend read with auto precharge cke cke write (write recovery) write write suspend write a write a suspend cke cke write with auto precharge power on precharge precharge p r e ( p r e c h a r g e t e r m i n a t i o n ) p r e ( p r e c h a r g e t e r m i n a t i o n ) r e a d w i t h w r i t e w i t h a u t o p r e c h a r g e a u t o p r e c h a r g e read b s t write r e a d w i t h a u t o p r e c h a r g e ( w r i t e r e c o v e r y ) w r i t e w i t h a u t o p r e c h a r g e write read (write recovery) pre cke c k e automatic sequenc e manual input note: after the auto refresh operation, precharge operation is performed automatically and enter the idle state s e l f e n t r y s e l f e x i t write recov e ry
IC42S16160 integrated circuit solution inc. 11 dr037-0a 9/05/2003 command truth table cke a11 symbol command n-1 n cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we ba a10 a9-a0 desl device deselect hxhxxxxxx nop no operation hxlhhhxxx mrs mode register set hxllllllv act bank activate hxl lhhvvv read read hxlhlhvlv reada read with auto precharge hxlhlhvhv writ write hxlhl lvlv writa write with auto precharge hxlhl lvhv pre precharge select bank hxl lhlvlx pall precharge all banks hxl lhlxhx bst burst stop hxlhhlxxx ref cbr (auto) refresh hhlllhxxx self self refresh hllllhxxx notes: h : high level l : low level x : high or low level (don?t care) v : valid data input dqm truth table cke symbol command n-1 n dqm enb data write / output enable h x l mask data mask / output disable h x h cke truth table cke symbol command current state n-1 n cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we addreess ? clock suspend mode entry activating hlxxxx x ? clock suspend any l lxxxx x ? clock suspend mode exit clock suspend lhxxxx x ref cbr refresh command idle hhlllh x self self refresh entry idle hllllh x ? self refresh exit self refresh lhlhhh x lhhxxx x ? power down entry idle hlxxxx x ? power down exit power down lhxxxx x
IC42S16160 12 integrated circuit solution inc. dr037-0a 9/05/2003 operation command table (1) current state command operation cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we address idle desl nop or power-down (2) hxxxx nop or bst nop or power-down (2) lhhx x read / reada illegal (3) lhlh ba, ca, a10 writ/writa illegal (3) lhll ba, ca, a10 act row active l l h h br, ra pre/pall nop l l h l ba, a10 ref/self refresh or self-refresh (4) lllhx mrs mode register set llll op-code row active desl nop h x x x x nop or bst nop l h h h x read/reada begin read : determine ap (5) lhlh ba, ca, a10 writ/writa begin write : determine ap (5) lhll ba, ca, a10 act illegal (3) llhh br, ra pre/pall precharge (6) llhl ba, a10 ref/self illegal l l l h x mrs illegal llll op-code read desl continue burst to end -> row active hxxxx nop continue burst to end -> row active lhhhx bst burst stop -> row active lhhlx read/reada term burst, new read : determine ap (7) lhlh ba, ca, a10 writ/writa term burst, start write : determine ap (7, 8) lhll ba, ca, a10 act illegal (3) llhh br, ra pre/pall term burst, precharging llhl ba, a10 ref/self illegal l l l h x mrs illegal llll op-code write desl continue burst to end -> write recovering hxxxx nop continue burst to end -> write recovering lhhhx bst burst stop -> row active lhhlx read/reada term burst, start read : determine ap (7, 8) lhlh ba, ca, a10 writ/writa term burst, new write : determine ap (7) lhll ba, ca, a10 act illegal (3) llhh br, ra pre/pall term burst, precharging (9) llhl ba, a10 ref/self illegal l l l h x mrs illegal llll op-code read with desl continue burst to end -> precharging hxxxx auto- nop continue burst to end -> precharging lhhhx precharge bst illegal l h h l x read/reada illegal (11) lhlh ba, ca, a10 writ/writa illegal (11) lhll ba, ca, a10 act illegal (3) llhh br, ra pre/pall illegal (11) llhl ba, a10 ref/self illegal l l l h x mrs illegal llll op-code
IC42S16160 integrated circuit solution inc. 13 dr037-0a 9/05/2003 operation command table (continue) current state command operation cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we address write with auto desl continue burst to end -> write recovering with auto precharge hxxxx precharge nop continue burst to end -> write recovering with auto precharge lhhh x bst illegal l h h l x read / reada illegal (11) lhlh ba, ca, a10 writ/writa illegal (11) lhll ba, ca, a10 act illegal (3, 11) llhh br, ra pre/pall illegal (3, 11) llhl ba, a10 ref/self illegal l l l h x mrs illegal llll op-code precharging desl nop -> enter idle after t rp hxxxx nop nop -> enter idle after t rp lhhhx bst nop -> enter idle after t rp lhhlx read/reada illegal (3) lhlh ba, ca, a10 writ/writa illegal (3) lhll ba, ca, a10 act illegal (3) llhh br, ra pre/pall nop -> enter idle after t rp llhl ba, a10 ref/self illegal l l l h x mrs illegal llll op-code row activating desl nop - > enter row active after t rcd hxxxx nop nop - > enter row active after t rcd lhhhx bst nop - > enter row active after t rcd lhhlx read/reada illegal (3) lhlh ba, ca, a10 writ/writa illegal (3) lhll ba, ca, a10 act illegal (3, 9) llhh br, ra pre/pall illegal (3) llhl ba, a10 ref/self illegal l l l h x mrs illegal llll op-code write desl nop -> enter row active after t dpl hxxxx recovering nop nop -> enter row active after t dpl lhhhx bst nop -> enter row active after t dpl lhhlx read/reada start read, determine ap (8) lhlh ba, ca, a10 writ/writa new write, determine ap lhll ba, ca, a10 act illegal (3) llhh br, ra pre/pall illegal (3) llhl ba, a10 ref/self illegal l l l h x mrs illegal llll op-code
IC42S16160 14 integrated circuit solution inc. dr037-0a 9/05/2003 operation command table (continue) current state command operation cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we address write desl nop -> enter precharge after t dpl hxxxx recovering nop nop -> enter precharge after t dpl lhhh x with auto bst nop -> enter precharge after t dpl lhhl x precharge read/reada illegal (3 ,8, 11) lhlh ba, ca, a10 writ/writa illegal (3,11) lhll ba, ca, a10 act illegal (3, 11) llhh br, ra pre/pall illegal (3, 11) llhl ba, a10 ref/self illegal l l l h x mrs illegal llll op-code auto desl nop enter idle after t rc hxxxx refreshing nop/bst nop enter idle after t rc lhhxx read/writ illegal l h l x x act/pre/pall illegal l l h x x ref/self/mrs illegal l l l x x mode desl nop -> enter idle after 2 clocks hxxxx register nop nop -> enter idle after 2 clocks lhhhx setting bst illegal l h h l x read/writ illegal l h l x x act/pre/pall/ illegal l l x x x ref/self/mrs notes: 1. all entries assume that cke was active (high level) during the preceding clock cycle. 2. if both banks are idle, and cke is inactive (low level), the device will enter power downmode. all input buffers except cke will be disabled. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address(ba), depending on the state of that bank. 4. if both banks are idle, and cke is inactive (low level), the device will enter self refresh mode. all input buffers except ck e will be disabled. 5. illegal if t rcd is not satisfied. 6. illegal if t ras is not satisfied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. must mask preceding data which don?t satisfy t dpl . 10. illegal if t rrd is not satisfied. 11. illegal for single bank, but legal for other banks in multi-bank devices.
IC42S16160 integrated circuit solution inc. 15 dr037-0a 9/05/2003 cke related command truth table (1) cke current state operation n-1 n cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we address self-refresh (s.r.) invalid, clk (n - 1)would exit s.r. hxxxxxx self-refresh recovery (2) lhhxxxx self-refresh recovery (2) lh l h h xx illegal l h l h l x x illegal l h l l x x x maintain s.r. llxxxxx self-refresh recovery idle after t rc hhhxxxx idle after t rc hh l h h xx illegal h h l h l x x illegal h h l l x x x begin clock suspend next cycle (5) hlhxxxx begin clock suspend next cycle (5) hl l h h xx illegal h l l h l x x illegal h l l l x x x exit clock suspend next cycle (2) lhxxxxx maintain clock suspend llxxxxx power-down (p.d.) invalid, clk (n - 1) would exit p.d. hxxxxx? exit p.d. -> idle (2) lhxxxxx maintain power down mode llxxxxx both banks idle refer to operations in operative command table hhhxxx? refer to operations in operative command table hh l h x x? refer to operations in operative command table hh l l h x? auto-refresh h h l l l h x refer to operations in operative command table hhllll op - code refer to operations in operative command table hlhxxx? refer to operations in operative command table hl l h x x? refer to operations in operative command table hl l l h x? self-refresh (3) hllllhx refer to operations in operative command table hlllll op - code power-down (3) lxxxxxx any state refer to operations in operative command table hhxxxxx other than begin clock suspend next cycle (4) hlxxxxx listed above exit clock suspend next cycle lhxxxxx maintain clock suspend llxxxxx notes: 1. h : hight level, l : low level, x : high or low level (don?t care). 2. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command other than exit. 3. power down and self refresh can be entered only from the both banks idle state. 4. must be legal command as defined in operative command table. 5. illegal if t srex is not satisfied.
IC42S16160 16 integrated circuit solution inc. dr037-0a 9/05/2003 initiallization before starting normal operation, the following power on sequence is necessary to prevent sdram from damged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high , dqn high and nop condition at the inputs. 2. maintain stable power, table clock , and nop input conditions for a minimum of 200us. 3. issue precharge commands for all bank. (pre or prea) 4. after all banks become idle state (after t rp ), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode regiser. after these sequence, the sdram is in idle state and ready for normal operation. programming the mode register the mode register is programmed by the mode register set command using address bits ba1 through a0 as data inputs. the register retains data until it is reprogrammed or the device loses power. the mode register has four fields; options : ba1 through a7 cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be asserted befor at least two clock cycles have elapsed. cas cas cas cas cas latency cas latency is the most critical parameter being set. it tells the device how many clocks must elapse before the data will be available. the value is determined by the frequency of the clock and the speed grade of the device. the value can be pro- grammed as 2 or 3. burst length burst length is the number of words that will be output or input in read or write cycle. after a read burst is completed, the output bus will become high impedance. the burst length is programmable as 1, 2, 4, 8 or full page. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. the order is programmable as either ?sequential? or ?interleave?. the method chosen will depend on the type of cpu in the system.
IC42S16160 integrated circuit solution inc. 17 dr037-0a 9/05/2003 mode register 0 0 1 0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 burst read and single write (for write through cach e) cas latency wt bl 000 00 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 burst read and burst write x = don?t care wt bl burst length bits2 - 0 wt = 1 wt = 0 000 001 010 011 100 101 110 111 1 2 4 8 r r r fullpage 1 2 4 8 r r r r wrap type 0 1 sequential interleave latency bits 6-4 cas iatency 000 001 010 011 100 101 110 111 r r 2 3 r r r r mode remark r : reserved a12 ba0 0 0 ba0 a12 0 0 0 ba1 0 b a1 cas latency
IC42S16160 18 integrated circuit solution inc. dr037-0a 9/05/2003 burst length and sequence burst of two starting address sequential addressing interleave addressing sequence (column address a0, binary) sequence (decimal) (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 burst of four starting address sequential addressing interleave addressing sequence (column address a1 - a0, binary) sequence (decimal) (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 burst of eight starting address sequential addressing interleave addressing sequence (column address a2 - a0, binary) sequence (decimal) (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1 ,2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6 ,7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
IC42S16160 integrated circuit solution inc. 19 dr037-0a 9/05/2003 address bits of bank-select and precharge ba0 ba1 result 0 0 select bank a ?activate ? command 0 1 select bank b ?activate? command 1 0 select bank c ?activate? command 1 1 select bank d ?activate? command 0 disable auto-precharge (end of burst) 1 enable auto - precharge (end of burst) ( activate command) a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 a11 ba0 ba1 result 0 0 0 precharge bank a 0 0 1 precharge bank b 0 1 0 precharge bank c 0 1 1 precharge bank d 1 x x precharge all banks ba0 ba1 result 0 0 enable read/write commands for bank a 0 1 enable read/write commands for bank b 1 0 enable read/write commands for bank c 1 1 enable read/write commands for bank d row ( precharge command) a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 r ow ( cas strobes) a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 co1. x: don't care a0 a0 a0
IC42S16160 20 integrated circuit solution inc. dr037-0a 9/05/2003 precharge the precharge command can be asserted anytime after t ras (min.) is satisfied. soon after the precharge command is asserted, the precharge operation is performed and the synchronous dram enters the idle state after t rp (min.) is satisfied. the parameter t rp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows. prechargee burst lengh= 4 clk command cas latency = 2 dq command cas latency = 3 dq (t ras is satisfied) hi - z q0 q3 q2 q1 pre q0 q3 q2 q1 read read t0 t1 t2 t3 t4 t5 t6 t7 pre hi - z in order to write all data to the memory cell correctly, the asynchronous parameter t dpl must be satisfied. the t dpl (min.) specification defines the earliest time that a precharge command can be asserted. the minimum number of clocks can be calculated by dividing t dpl (min.) with the clock cycle time. in summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid. in the following table, minus means clocks before the reference; plus means time after the reference. cas cas cas cas cas latency read write 2-1+ t dpl ((min.) 3-2+ t dpl ((min.)
IC42S16160 integrated circuit solution inc. 21 dr037-0a 9/05/2003 auto precharge during a read or write command cycle, a10 controls whether auto precharge is selected. if a10 is high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begins automatically. in the write cycle, t dal (min.) must be satisfied before asserting the next activate command to the bank being precharged. when using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. once auto precharge has started, an activate command to the bank can be asserted after t rp has been satisfied. a read or write command without auto - precharge can be terminated in the midst of a burst operation. however, a read or write command with auto - precharge can not be interrupted by the same bank commands before the entire burst opera- tion is completed. therefore use of the same bank read, write, precharge or burst stop command is prohibited during a read or write cycle with auto - precharge. it should be noted that the device will not respond to the auto - precharge com- mand if the device is programmed for full page burst read or write cycles. the timing when the auto precharge cycle begins depends both on both the cas iatency programmed into the mode reg- ister and whether the cycle is read or write. read with auto precharge during a reada cycle, the auto precharge begins one clock earlier (cl = 2) or two clocks earlier (cl = 3) than the last word output. read with auto precharge burst lengh = 4 clk command cas latency = 2 dq command cas latency = 3 dq r emark reada means read with auto precharge hi - z auto precharge starts qb0 qb3 qb2 qb1 reada b reada b t0 t1 t2 t3 t4 t5 t6 t7 auto precharge starts hi - z t 8 qb0 qb3 qb2 qb1 no new command to bank b no new command to bank b
IC42S16160 22 integrated circuit solution inc. dr037-0a 9/05/2003 write with auto precharge during a write cycle, the auto precharge starts at the timing that is equal to the value of t dpl (min.) after the last data word input to the device. in summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. in the table below, minus means clocks before the reference; plus means clocks after the reference. cas cas cas cas cas latency read write 2-1+ t dpl ((min.) 3-2+ t dpl ((min.) write with auto prechrge burst lengh = 4 clk command cas latency = 2 dq command cas latency = 3 dq r emark writa means write with auto precharge hi - z db0 db3 db2 db1 writa b writa b t0 t1 t 2 t3 t4 t5 t6 t7 hi - z_ t8 t dpl t dpl db0 db3 db2 db1 auto precharge starts auto precharge starts
IC42S16160 integrated circuit solution inc. 23 dr037-0a 9/05/2003 read / write command interval read to read command interval during a read cycle when a new read command is asserted, it will be effective after the cas latency, even if the previous read operation has not completed. read will be interrupted by another read. each read command can be asserted in every clock without any restriction. write to write command interval during a write cycle, when a new write command is asserted, the previous burst will terminate and the new burst will begin with a new write command. write will be interrupted by another write. each write command can be asserted in every clock without any restriction. read to read command interval burst lengh=4, cas latency= 2 clk c ommand dq qa0 qb2 qb1 qb0 read a t0 t1 t2 t3 t4 t5 t6 t7 hi-z_ t 8 1 cycle qb3 read b burst lengh=4, cas latency= 2 clk c ommand dq qa0 qb2 qb1 qb0 write a t0 t1 t2 t3 t4 t5 t6 t7 hi-z_ t 8 1 cycle qb3 write b write to write command interval
IC42S16160 24 integrated circuit solution inc. dr037-0a 9/05/2003 write to read command interval the write command to read command interval is also a minimum of 1 cycle. only the write data before the read command will be written. the data bus must be hi-z at least one cycle prior to the first d out . write to read command interval burst lengh=4 clk command cas latency=2 dq command cas latency=3 dq qb0 qb3 qb2 qb1 write a write a t0 t1 t2 t3 t4 t5 t6 t7 t8 qb0 qb3 qb2 qb1 1 cycle read b da0 read b da0 hi-z hi-z read to write command interval during a read cycle, read can be interrupted by write. dqm must be in high at least 3 clocks prior to the write command. there is a restriction to avoid a data conflict. the data bus must be hi-z using dqm before write.
IC42S16160 integrated circuit solution inc. 25 dr037-0a 9/05/2003 read to write command interval cas latency=2 clk command d qm dq hi-z d0 d3 d2 d1 read t0 t1 t2 t3 t4 t5 t6 t7 t8 1 cycle write burst length=8, cas latency= 2 clk c ommand dqm dq q0 read t0 t1 t2 t3 t4 t5 t6 t7 t8 write t9 necessary q2 q1 d0 d2 d1 hi-z is example: burst length=4, cas latency= 3 clk c ommand dqm dq read t0 t1 t2 t3 t4 t5 t6 t7 t8 write necessary d0 d2 d1 hi-z is q2
IC42S16160 26 integrated circuit solution inc. dr037-0a 9/05/2003 burst termination there are two methods to terminate a burst operation other than using a read or a write command. one is the burst stop command and the other is the precharge command. burst stop command during a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus goes to high-impedance after the cas latency from the burst stop command. during a write burst, when the burst stop command is issued, the burst write data are termained and data bus goes to hi- z at the same clock with the burst stop command. burst termination burst lengh=x, cas intency=2 ,3 clk command cas latency=2 dq c as latency=3 dq q0 q2 q1 read t0 t1 t2 t3 t4 t5 t6 t7 bst hi-z q0 q2 q1 hi-z remark bst: burst stop command remark bst: burst command burst lengh=x, cas latency=2 ,3 clk command c as latency=2,3 dq q0 q2 q1 write t0 t1 t2 t3 t4 t5 t6 t7 bst hi-z_ q0
IC42S16160 integrated circuit solution inc. 27 dr037-0a 9/05/2003 precharge termination precharge termination in read cycle during read cycle, the burst read operation is terminated by a precharge command. when the precharge command is issued, the burst read operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. when cas latency is 2, the read data will remain valid until one clock after the precharge command. when cas latency is 3, the read data will remain valid until two clocks after the precharge command. precharge termination in read cycle burst lengh= x clk command c as latency=2 d q hi-z read t0 t1 t2 t3 t4 t5 t6 t7 t8 pre act d q read pre act t rp c as latency=3 q0 q3 q2 q1 hi-z q0 q3 q2 q1 command t rp
IC42S16160 28 integrated circuit solution inc. dr037-0a 9/05/2003 precharge termination in write cycle during write cycle, the burst write operation is terminated by a precharge command. when the precharge command is issued, the burst write operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. the dqm must be high to mask invalid data in. during write cycle, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. precharge termination in write cycle burst lengh = x clk command cas latency = 2 dqm hi - z write t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp pre act d q write pre act t rp cas latency = 3 hi - z d0 d3 d2 d1 d0 d3 d2 d1 dqm d4 d4 c ommand dq
IC42S16160 integrated circuit solution inc. 29 dr037-0a 9/05/2003 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 clk cke cs ras cas we bs0,1 a10 add dqm dq command mode register set command all banks precharge command t rp t rsc hi-z address key mode register set
IC42S16160 30 integrated circuit solution inc. dr037-0a 9/05/2003 ac parameters for write timing (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t ch t cl t cks t cms t cmh t as t ah begin auto precharge bank a begin auto precharge bank b t ckh t ck2 c lk c ke cs r as c as we * bs0 a 10 a dd d qm d q t rcd t rrd t rc t dal qaa0 qaa1 qaa2 qaa3 qba0 qba1 qba2 qba3 qab0 qab1 qab2 qab3 activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write without auto precharge command bank a t ds t dh t dpl rp t precharge command bank a activate command bank a burst length=4, cas latency=3 activate command bank b
IC42S16160 integrated circuit solution inc. 31 dr037-0a 9/05/2003 ac parameters for write timing (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t ch t cl t cks t cms t cmh t as t ah begin auto precharge bank a begin auto precharge bank b t ckh t ck3 clk cke cs ras cas we a10 add dqm dq t rcd t rrd rc t dal qaa0 qaa1 qaa2 qaa3 qba0 qba1 qba2 qba3 qab0 qab1 qab2 qab3 activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write without auto precharge command bank a t ds t dh t dpl rp t precharge command bank a activate command bank a burst length=4, cas latency=3 *bs0
IC42S16160 32 integrated circuit solution inc. dr037-0a 9/05/2003 ac parameters for read timing (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke cs ras cas we a10 add d qm dq burst length=2, cas latency=2 t ch t cl t ck2 begin auto precharge bank b t ckh t cks t cms t cmh t ah t as t rrd t ras t rc t rcd t ac2 t lz t oh t ac2 t oh t hz t rp t hz hi-z activate command bank a read command bank a activate command bank b read with auto precharge bank b precharge command bank a activate command bank a qaa0 qaa1 qba0 qba1 command * bs0
IC42S16160 integrated circuit solution inc. 33 dr037-0a 9/05/2003 ac parameters for read timing (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 clk cke cs ras cas we a10 add d qm dq burst length=2, cas latency=3 t lz t hz hi-z activate command bank a read command bank a activate command bank b read with auto precharge bank b precharge command bank a activate command bank a t ch t cl t cks t ck3 t cms t cmh t ah t as t rrd t ras t rc t rp t rcd t ac3 t oh t ac3 qaa0 qaa1 qba0 qba1 t oh t hz command t ckh begin auto precharge bank b *bs0
IC42S16160 34 integrated circuit solution inc. dr037-0a 9/05/2003 power on sequence and auto refresh (cbr) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq high level is required minimum of 8 refresh cycles are required t rsc t rp high level is necessary t rc address key inputs be stable for 200us precharge all banks must command 1st auto command refresh 2nd auto refresh command mode set command command register hi-z b s0, 1
IC42S16160 integrated circuit solution inc. 35 dr037-0a 9/05/2003 clock suspension during burst read (using cke) (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t hz activate bank a command read bank a command clock 2 cycles hi-z qaa0 qaa1 qaa2 qaa3 raa caa raa t ck2 clock suspended 1 cycle suspended clock 3 cycles suspended burst length=4, cas latency=2 * bs0
IC42S16160 36 integrated circuit solution inc. dr037-0a 9/05/2003 clock suspension during burst read (using cke) (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t hz activate bank a command read bank a command clock 2 cycles hi-z qaa0 qaa1 qaa2 qaa3 raa raa t ck3 clock suspended 1 cycle suspended clock 3 cycles suspended burst length=4, cas latency=3 caa * bs0
IC42S16160 integrated circuit solution inc. 37 dr037-0a 9/05/2003 clock suspension during burst write (using cke) (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq activate bank a command write bank a command clock 2 cycles hi-z raa caa raa t ck2 clock suspended 1 cycle suspended clock 3 cycles suspended burst length=4, cas latency=2 daa0 daa1 daa2 daa3 * bs0
IC42S16160 38 integrated circuit solution inc. dr037-0a 9/05/2003 clock suspension during burst write (using cke) (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq raa raa t ck3 burst length=4, cas latency=3 caa activate bank a command write bank a command clock 2 cycles hi-z clock suspended 1 cycle suspended clock 3 cycles suspended daa0 daa1 daa2 daa3 * bs0
IC42S16160 integrated circuit solution inc. 39 dr037-0a 9/05/2003 power down mode and clock mask bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq raa raa t ck2 burst length=4, cas latency=2 activate bank a command power down mode entry power down bank a hi-z active standby read clock mask caa t cks t ckh valid t cks raa qaa0 qaa1 qaa2 mode exit command start clock mask end precharge command power down mode entry precharge standby power mode down exit command * bs0 qaa3
IC42S16160 40 integrated circuit solution inc. dr037-0a 9/05/2003 auto refresh (cbr) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck2 burst length=4, cas latency=2 precharge all banks command cbr refresh hi-z cbr refresh command activate command read raa caa raa q0 q1 q2 q3 command command t rp t rc t rc * bs0, 1
IC42S16160 integrated circuit solution inc. 41 dr037-0a 9/05/2003 self refresh (entry and exit) bs1=?l?, bank c,d = idle clock can be stopped at cke=low. if clock is stopped, it must be restarted/stable for 4 clock cycles before cke=high t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 a dd d qm dq t srx all banks self refresh hi-z self refresh exit self refresh entry exit t rc t cks t srx t cks t rc must be idle self refresh entry activate command clk can be stopped ** *bs0
IC42S16160 42 integrated circuit solution inc. dr037-0a 9/05/2003 random column read (page with same bank) (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 a dd d qm dq t ck2 burst length=4, cas latency=2 precharge bank a command read hi-z activate read raa qad0 command command raa caa raa cab cac rad rad cad qaa0 qaa1 qaa2 qaa3 qab0 qab1 qac0 qac1 qac2 qac3 qad1 qad2 qad3 bank a read command bank a read command bank a precharge command bank a bank a command bank a *bs0
IC42S16160 integrated circuit solution inc. 43 dr037-0a 9/05/2003 random column read (page with same bank) (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck3 burst length=4, cas latency=3 activate bank a command read hi-z activate read command command raa caa cab cac rad cad qac2 qac3 qaa0 qaa1 qaa2 qaa3 qab0 qab1 qac0 qac1 bank a read command bank a precharge command bank a bank a command bank a rad read command bank a raa *bs0
IC42S16160 44 integrated circuit solution inc. dr037-0a 9/05/2003 random column write (page with same bank) (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck2 burst length=4, cas latency=2 activate bank b command write hi-z activate write command command ra ca ra cb cc rd cd dc2 dc3 da1 da2 da3 db0 db1 dc0 dc1 bank b write command bank b precharge command bank b bank b command bank b write command bank b rd dd2 dd3 dd0 dd1 da0 *bs0
IC42S16160 integrated circuit solution inc. 45 dr037-0a 9/05/2003 random column write (page with same bank) (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck burst length=4, cas latency=3 activate bank b command write hi-z activate command ra ca ra cb cc cd rd bank b write command bank b precharge command bank b command bank b write command bank b rd write command bank b dc2 dc3 da1 da2 da3 db0 db1 dc0 dc1 da0 dd0 dd1 *bs0
IC42S16160 46 integrated circuit solution inc. dr037-0a 9/05/2003 random row read (interleaving banks) (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck2 burst length=8, cas latency=2 activate bank b command read hi-z command qaa0 qaa1 qba1 qba2 qba3 qba4 qba5 qba6 qba7 bank b activate command bank a active command bank b read command bank a qbb1 qbb0 qba0 read command bank b qaa3 qaa4 qaa5 qaa6 qaa7 qaa2 precharge command bank b t rcd t ac2 t rp high *bs0
IC42S16160 integrated circuit solution inc. 47 dr037-0a 9/05/2003 random row read (interleaving banks) (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck3 burs tlength=8, cas latency=3 activate bank b command read hi-z command qaa0 qaa1 qba1 qba2 qba3 qba4 qba5 qba6 qba7 bank b activate command bank a precharge command bank b qbb0 qba0 read command bank b qaa3 qaa4 qaa5 qaa6 qaa7 qaa2 read command bank a t rcd t ac3 t rp high activate bank b command precharge command bank a *bs0
IC42S16160 48 integrated circuit solution inc. dr037-0a 9/05/2003 random row write (interleaving banks) (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck2 burst length=8, cas latency=2 activate bank a command write hi-z command qba0 qba1 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 bank a activate command bank b active command bank a write command bank b qab3 qab2 qaa0 write command bank a qba3 qba4 qba5 qba6 qba7 qba2 precharge command bank a t rcd t rp high t dpl qab0 qab1 qab4 precharge command bank b *bs0
IC42S16160 integrated circuit solution inc. 49 dr037-0a 9/05/2003 random row write (interleaving banks) (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck burst length=8, cas latency=3 activate bank a command write hi-z command qaa7 qba0 qaa0 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 bank a activate command bank b qab2 qab1 activate command bank a qba2 qba3 qba4 qba5 qba6 qba1 write command bank b rba t rp high t dpl t dpl qbb7 qab0 qab3 write command bank a precharge command bank a precharge command bank b *bs0
IC42S16160 50 integrated circuit solution inc. dr037-0a 9/05/2003 read and write cycle (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck2 burst length=4, cas latency=2 activate bank a command write hi-z command dab3 qac0 qaa0 qaa1 qaa2 qaa3 dab0 dab1 bank a write command bank a read command bank a qac3 qac1 the read data the write data is masked with a zero clock raa raa cab cac caa latency is masked with two clocks latency *bs0
IC42S16160 integrated circuit solution inc. 51 dr037-0a 9/05/2003 read and write cycle (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck3 burst length=4, cas latency=3 activate bank a command read hi-z command dab3 qac0 qaa0 qaa1 qaa2 qaa3 dab0 dab1 bank a write command bank a qac3 qac1 the read data the write data is masked with a zero clock raa latency is masked with two clock latency raa cab caa cac read command bank a *bs0
IC42S16160 52 integrated circuit solution inc. dr037-0a 9/05/2003 interleaved column read cycle (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck2 burst length=4, cas latency=2 activate bank a command read hi-z command qbb1 qbd0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 bank a read command bank b qbd2 qbd1 precharge ra ra ra cb ra ca cb cc cb cd qab1 qbc0 qbc1 qbd3 activate command bank b read command bank b qbb0 qab0 read command bank b read command bank a read command bank b precharge command bank a command bank b t rcd t ac2 *bs0
IC42S16160 integrated circuit solution inc. 53 dr037-0a 9/05/2003 interleaved column read cycle (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z qbb1 qab2 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qab3 precharge ra ra ra ca ra ca cb cc cb qab1 qbc0 qbc1 read command bank a read command bank b qbb0 qab0 read command bank b read command bank b read command bank a precharge command bank b command bank a t rrd activate command bank b t rcd t ac3 *bs0
IC42S16160 54 integrated circuit solution inc. dr037-0a 9/05/2003 interleaved column write cycle (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck2 burst length=4, cas latency=2 activate bank a command hi-z dbb1 dbd0 daa0 daa1 daa2 daa3 dba0 dba1 dbd1 precharge ra ra ra ca ra ca cb cc cb dab1 dbc0 dbc1 write command bank a write command bank b dbb0 dab0 command write command bank b write command bank a precharge command bank a command bank b t rrd activate command bank b t rcd t rp cb dbd2 dbd3 write bank b t dpl write command bank b *bs0
IC42S16160 integrated circuit solution inc. 55 dr037-0a 9/05/2003 interleaved column write cycle (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z qbb1 qbd0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qbd1 precharge ra ra ra ca ra ca cb cc cb qab1 qbc0 qbc1 write command bank a write command bank b qbb0 qab0 write command bank b write command bank b write command bank a write command bank b command bank a t rrd activate command bank b t rcd cd t dpl t rp qbd2 qbd3 t dpl precharge command bank b *bs0
IC42S16160 56 integrated circuit solution inc. dr037-0a 9/05/2003 auto precharge after read burst (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck2 burst length=4, cas latency=2 activate bank a command hi-z qba3 qbb0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qbb1 read with ra ra ca ra ca cb rb cb qab3 qab0 qab1 activate command bank b qba2 qab2 read with command bank a activate command bank b read with command bank b activate command bank a command bank a read with auto precharge bank b rc qbb2 qbb3 rb rc ra cc qac0 qac2 read bank a command command qac1 auto precharge auto precharge auto precharge start auto precharge bank b start auto precharge bank a start auto precharge bank b high *bs0
IC42S16160 integrated circuit solution inc. 57 dr037-0a 9/05/2003 auto precharge after read burst (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z qba3 qaa0 qaa1 qaa2 qaa3 qba0 qba1 ra ra ra qab3 qab0 qab1 read command bank a read with command bank b qba2 qab2 command bank a activate command bank b qbb0 ra ca ca rbb cb auto precharge start auto precharge bank b start auto bank a start auto precharge bank b high rb cb qbb1 qbb2 activate command bank b write with auto precharge auto precharge command bank b read with rb precharge *bs0
IC42S16160 58 integrated circuit solution inc. dr037-0a 9/05/2003 auto precharge after write burst (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck2 burst length=4, cas latency=2 activate bank a command hi-z qba3 qbb0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qbb1 ra ra ra qab3 qab0 qab1 write command bank a write with command bank b qba2 qab2 write with command bank a activate command bank b write with command bank b activate command bank b qbb2 qbb3 rb ra ca cb ca rb cb auto precharge auto precharge auto precharge start auto precharge bank b start auto precharge bank a start auto precharge bank b high rc rc cc qac0 qac1 qac2 qac3 activate command bank a write with auto precharge bank a start auto precharge bank a *bs0
IC42S16160 integrated circuit solution inc. 59 dr037-0a 9/05/2003 auto precharge after write burst (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z qba3 qaa0 qaa1 qaa2 qaa3 qba0 qba1 ra ra ra qab3 qab0 qab1 read command bank a read with command bank b qba2 qab2 command bank a activate command bank b qbb0 ra ca ca rbb cb auto precharge start auto precharge bank b start auto bank a start auto precharge bank b high rb cb qbb1 qbb2 activate command bank b write with auto precharge auto precharge command bank b read with rb precharge qbb3 *bs0
IC42S16160 60 integrated circuit solution inc. dr037-0a 9/05/2003 full page read cycle (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck2 burst length=full page, cas latency=2 activate bank a command read hi-z command ra qaa+1 bank a the burst counter wraps burst stop read command bank b qaa full page burst operation does not ra ca rb t rp high activate command bank b ra rb ca qaa+2 qaa-2 qaa-1 qaa qaa+1 qba qba+1 qba+2 qba+3 qba+4 qba+51 qba+6 activate command bank b from the highest order page address back to zero during this time interval terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address command precharge command bank b ra *bs0
IC42S16160 integrated circuit solution inc. 61 dr037-0a 9/05/2003 full page read cycle (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck3 burst length=full page, cas latency=3 activate bank a command read hi-z command ra qaa+1 bank a the burst counter wraps burst stop read command bank b qaa full page burst operation ra ca rb high activate command bank b ra rb ca qaa+2 qaa-2 qaa-1 qaa qaa+1 qba0 qba+1 qba+2 qba+3 qba+4 qba+5 activate command bank b from the highest order page address back to zero during this time interval command precharge command bank b does not teminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address ra *bs0
IC42S16160 62 integrated circuit solution inc. dr037-0a 9/05/2003 full page write cycle (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command write hi-z command ra qaa+1 bank a the burst counter wraps burst stop write command bank b qaa full page burst operation ra ca rb t bdl high activate command bank b ra rb ca qaa+2 qaa+3 qaa-1 qaa qaa+1 qba qba+1 qba+2 qba+3 qba+4 qba+5 activate command bank b from the highest order page address back to zero during this time interval command precharge command bank b does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address qba+6 data is ignored ra *bs0
IC42S16160 integrated circuit solution inc. 63 dr037-0a 9/05/2003 full page write cycle (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck3 burst length=full page, cas latency=3 activate bank a command write hi-z command ra daa+1 bank a the burst counter wraps burst stop write command bank b daa full page burst operation ra t bdl high activate command bank b daa+2 daa+3 daa-1 daa daa+1 dba dba+1 dba+2 dba+3 dba+4 dba+5 activate command bank b from the highest order page address back to zero during this time interval command precharge command bank b does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address ra rb ca ra ca rb data is ignored. *bs0
IC42S16160 64 integrated circuit solution inc. dr037-0a 9/05/2003 burst read and single write operation bs1=?l?, bank c,d = idle hi-z t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm t ck2 burst length=4, cas latency=2 raa raa high activate caa cab cad dq command bank a read command bank a single write single write read command bank a dqs are masked cac cae command bank a command bank a single write command bank a dqs are masked * bs0
IC42S16160 integrated circuit solution inc. 65 dr037-0a 9/05/2003 full page random column read bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we bs a10 add d qm dq t ck2 burst length=full page, cas latency=2 activate bank a command activate hi-z command ra qba0 bank b read command bank b qaa0 ra activate command bank b qab0 qab1 qbb0 qbb1 qac0 qac1 qac2 qbc0 qbc1 qbc2 read command bank a precharge cc cc rb ra ra ca ca cb cb rb t rp read command bank b read command bank a read command bank a read command bank b command bank b (precharge termination) (bank d)
IC42S16160 66 integrated circuit solution inc. dr037-0a 9/05/2003 full page random column write bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command activate hi-z command ra qba0 bank b write command bank b qaa0 ra activate command bank b qab0 qab1 qbb0 qbb1 qac0 qac1 qac2 qbc0 qbc1 qbc2 write command bank a precharge cc cc rb ra ra ca ca cb cb rb t rp write command bank b write command bank a write command bank a write command bank b command bank b (precharge termination) write data is masked (bank d) *bs0
IC42S16160 integrated circuit solution inc. 67 dr037-0a 9/05/2003 precharge termination of a burst (1 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck2 burst length=8, cas latency=2 activate bank a command write hi-z command raa bank a activate command bank a read command bank a rac cab rab rab rac precharge termination of a write burst. write data is masked. precharge command read command bank a precharge command bank a precharge termination high raa cac caa qaa1 qaa0 qaa2 da3 qab0 qab1 qab2 qac0 qac1 qac2 t dpl t rp t rp t rp bank a of a read burst. activate command bank a precharge command bank a *bs0
IC42S16160 68 integrated circuit solution inc. dr037-0a 9/05/2003 precharge termination of a burst (2 of 2) bs1=?l?, bank c,d = idle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq t ck3 activate bank a command write hi-z command raa bank a activate command bank a cab rab rab rac precharge command read command bank a high raa rac caa daa1 daa0 qab0 qab1 qab2 qab3 t dpl t rp bank a activate command bank a activate command bank a t rcd t rp write data is masked precharge termination of a write burst. precharge termination of a read burst. t ras *bs0 burst length=8, cas latency= 3
IC42S16160 integrated circuit solution inc. 69 dr037-0a 9/05/2003 ordering information commercial range: 0 c to 70 c speed (ns) order part no. package 6 IC42S16160-6tg 400mil tsop-2(pb-free package) 7 IC42S16160-7tg 400mil tsop-2(pb-free package) ordering information industrial temperature range: -40 c to 85 c speed (ns) order part no. package 6 IC42S16160-6tig 400mil tsop-2(pb-free package) 7 IC42S16160-7tig 400mil tsop-2(pb-free package) integrated circuit solution inc. headquarter: no.2, technology rd. v, science-based industrial park, hsin-chu, taiwan, r.o.c. tel: 886-3-5780333 fax: 886-3-5783000 branch office: 7f, no. 106, sec. 1, hsin-tai 5 th road, hsichih taipei county, taiwan, r.o.c. tel: 886-2-26962140 fax: 886-2-26962252 http://www.icsi.com.tw

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